loop lock
英 [luːp lɒk]
美 [luːp lɑːk]
网络 环阻
双语例句
- The loop is a second order phase lock loop, consisting of an interpolator, a timing error detector and a loop filter.
环路为反馈结构，包括插值器、时钟误差检测和环路滤波器三个部分。 - The coherent delay lock loop is shown to have a major advantage, for a relatively high fading bandwidth, it has a zero tracking error, while a noncoherent delay lock loop has bias error of up to ten of meters.
对于大的衰减带宽，相干延迟锁定环路的多径跟踪误差为零，而非相干延迟所定环路有10m左右误差，载波相位的测量无误差； - When the system is in burst mode, so long as the loop is locked, the locked frequency value is saved in LPF ( Low Pass Filter) of PLL ( Phase Lock Loop).
当系统工作于突发模式时，只要环路有锁定的情况发生，则锁定的频率点将保存在环路滤波电容中，保证了对于有效信号组信号相位的快速锁定。 - Main performance index of the phase-locked loop lock is short time, small synchronous error, suitable frequency.
锁相环的主要性能指标是锁定时间短、同步误差小，适用频带适当。 - A digital phase-locked loop ( DPLL) based on a new digital phase-frequency detector is presented. The self-calibration technique is employed to acquire wide lock range, low jitter, and fast acquisition.
提出了一种数字锁相环（DPLL），它的相频检测器采用全新的设计方法和自校准技术，具有工作频率范围宽，抖动低，快速锁定的优点。 - The phase-locked loop frequency synthesizer is a kind of phase lock installment and it is a kind of separate gap frequency code generator with high stability frequency.
锁相环频率合成器是一种相位锁定装置，是一种频率稳定度较高的离散间隔型频率信号发生器。 - Study of loop of delay lock phase
延迟锁相环的研究 - Delay phase ‐ locked loop compared to phase lock loop, has characteristics of better stability, smaller clock jitter.
延时锁相环与锁相环相比，具有更好的稳定性，更小的时钟抖动等特点。 - GPS/ INS integration systems are widely used in different fields. Since GPS receiver carrier loop has lost lock during maneuver, the velocity aiding signal of code loop is derived from the inertial navigation system.
GPS／惯性导航组合系统目前正得到越来越广泛的应用，但GPS接收机载波环失锁时，码环的速率辅助信息来自惯导系统。 - In the input interface circuit, contrived all digital phase-locked loop ( ADPLL) with high accuracy which can exactly track and lock the frequency of power grid, in order to meet integer-cycle sampling or reduce the degree of non-integer-cycle sampling, so decrease measurement error.
在输入接口电路中，设计高精度全数字锁相环实现对电网频率进行精密跟踪锁定，使得达到整周期采样或减小非整周期采样的程度以减小测量误差。